NihilismAbsurdism.Blogspot.com

"The Absurd" refers to the conflict between the human tendency to seek inherent meaning in life and the human inability to find any.

Nihilism : from the Latin nihil, nothing) is the philosophical doctrine suggesting the negation of one or more putatively meaningful aspects of life

Saturday, June 25, 2011

Current Processors Chart

486 | 586 / 686 | 786 | Current Desktop | Server

This list is not comprehensive. Server chips have been moved to their own page.

AMD Desktop | Intel Desktop

AMD Desktop


Athlon 64 (Socket 754)
AMD
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Athlon 64 ??? MMX 3DNow! SSE SSE2
(Clawhammer)
(64-bit on-Die unbuffered DDR PC2700 mem controller; 4GB max)
[cancelled]		754 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		Socket 75464KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		? million
0.13µm process
104mm² die
AMD
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Athlon 64 2800+ MMX 3DNow! SSE SSE2
(Clawhammer)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
March 30, 2004 - {$178}		754 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.5v		Socket 75464KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		106 million
0.13µm process
193mm² die
Athlon 64 3000+ MMX 3DNow! SSE SSE2
(Clawhammer)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
December 15, 2003 - {$218}		754 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.5v		Socket 75464KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		106 million
0.13µm process
193mm² die
Athlon 64 3200+ MMX 3DNow! SSE SSE2
(Clawhammer)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
September 23, 2003 - {$417}		754 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.5v		Socket 75464KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		106 million
0.13µm process
193mm² die
Athlon 64 3400+ MMX 3DNow! SSE SSE2
(Clawhammer)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
January 6, 2004 - {$417}		754 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.5v		Socket 75464KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		106 million
0.13µm process
193mm² die
Athlon 64 3700+ MMX 3DNow! SSE SSE2
(Clawhammer)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
June 1, 2004 - {$710}		754 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v		Socket 75464KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		106 million
0.13µm process
193mm² die

Athlon 64 2800+ MMX 3DNow! SSE SSE2
(Newcastle)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
July, 2004		754 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.5v		Socket 75464KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		68.5 million
0.13µm process
144mm² die
Athlon 64 3000+ MMX 3DNow! SSE SSE2
(Newcastle)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
July, 2004 - {$218}		754 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.5v		Socket 75464KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		68.5 million
0.13µm process
144mm² die
Athlon 64 3200+ MMX 3DNow! SSE SSE2
(Newcastle)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
July, 2004 - {$278}		754 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.5v		Socket 75464KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		68.5 million
0.13µm process
144mm² die
Athlon 64 3400+ MMX 3DNow! SSE SSE2
(Newcastle)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
July, 2004 - {$417}		754 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v		Socket 75464KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		68.5 million
0.13µm process
144mm² die
AMD
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Sempron 2600+ MMX 3DNow! SSE SSE2
(Paris)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
(32-bit only)
2005		754 pins
1200MHz (200x6)
(64-bit dual-pumped bus)
1.5v		Socket 75464KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		? million
0.13µm process
118mm² die
Sempron 2800+ MMX 3DNow! SSE SSE2
(Paris)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
(32-bit only)
2005		754 pins
1400MHz (200x7)
(64-bit dual-pumped bus)
1.5v		Socket 75464KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		? million
0.13µm process
118mm² die
Sempron 3000+ MMX 3DNow! SSE SSE2
(Paris)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
(32-bit only)
2005		754 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
1.5v		Socket 75464KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		? million
0.13µm process
118mm² die
Sempron 3000+ MMX 3DNow! SSE SSE2
(Paris)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
(32-bit only)
2005		754 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.4v		Socket 75464KB data (2-way)
64KB instruction (2-way)
128KB on-Die unified L2 (16-way exclusive)		? million
0.13µm process
118mm² die
Sempron 3100+ MMX 3DNow! SSE SSE2
(Paris)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
(32-bit only)
July 28, 2004 - {$126}		754 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.5v		Socket 75464KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		? million
0.13µm process
118mm² die
Sempron 3300+ MMX 3DNow! SSE SSE2
(Paris)
(64-bit on-Die unbuffered DDR PC3200 mem controller; 4GB max)
(32-bit only)
1Q 2005		754 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.5v		Socket 75464KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		? million
0.13µm process
118mm² die

Sempron 2500+ MMX 3DNow! SSE SSE2 SSE3
(Palermo)
(64-bit on-Die unbuffered DDR mem controller)
July 7, 2005		754 pins
1400MHz (200x7)
(64-bit dual-pumped bus)
1.4v		Socket 75464KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		77 million
0.09µm process
84mm² die
Sempron 2600+ MMX 3DNow! SSE SSE2 SSE3
(Palermo)
(64-bit on-Die unbuffered DDR mem controller)
(32-bit only)
February 15, 2005		754 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
1.4v		Socket 75464KB data (2-way)
64KB instruction (2-way)
128KB on-Die unified L2 (16-way exclusive)		77 million
0.09µm process
84mm² die
Sempron 2800+ MMX 3DNow! SSE SSE2 SSE3
(Palermo)
(64-bit on-Die unbuffered DDR mem controller)
(32-bit only)
February 15, 2005		754 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
1.4v		Socket 75464KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		77 million
0.09µm process
84mm² die
Sempron 3000+ MMX 3DNow! SSE SSE2 SSE3
(Palermo)
(64-bit on-Die unbuffered DDR mem controller)
(32-bit only)
February 15, 2005		754 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.4v		Socket 75464KB data (2-way)
64KB instruction (2-way)
128KB on-Die unified L2 (16-way exclusive)		77 million
0.09µm process
84mm² die
Sempron 3100+ MMX 3DNow! SSE SSE2 SSE3
(Palermo)
(64-bit on-Die unbuffered DDR mem controller)
(32-bit only)
February 15, 2005		754 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.4v		Socket 75464KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		77 million
0.09µm process
84mm² die
Sempron 3300+ MMX 3DNow! SSE SSE2 SSE3
(Palermo)
(64-bit on-Die unbuffered DDR mem controller)
(32-bit only)
April 18, 2005		754 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		Socket 75464KB data (2-way)
64KB instruction (2-way)
128KB on-Die unified L2 (16-way exclusive)		77 million
0.09µm process
84mm² die
Sempron 3400+ MMX 3DNow! SSE SSE2 SSE3
(Palermo)
(64-bit on-Die unbuffered DDR mem controller)
(32-bit only)
July 29, 2005 - {$134}		754 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		Socket 75464KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		77 million
0.09µm process
84mm² die


Athlon 64 (Socket 939)
AMD
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Athlon 64 2800+ MMX 3DNow! SSE SSE2
(Newcastle)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
[not released]		939 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.5v		Socket 93964KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		68.5 million
0.13µm process
144mm² die
Athlon 64 3000+ MMX 3DNow! SSE SSE2
(Newcastle)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
[not released]		939 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.5v		Socket 93964KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		68.5 million
0.13µm process
144mm² die
Athlon 64 3500+ MMX 3DNow! SSE SSE2
(Newcastle)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
June 1, 2004 - {$500}		939 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.5v		Socket 93964KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		68.5 million
0.13µm process
144mm² die
Athlon 64 3800+ MMX 3DNow! SSE SSE2
(Newcastle)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
June 1, 2004 - {$720}		939 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v		Socket 93964KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		68.5 million
0.13µm process
144mm² die

Athlon 64 4000+ MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
October 19, 2004 - {$729}		939 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v		Socket 93964KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		106 million
0.13µm process
193mm² die

Athlon 64 4000+ MMX 3DNow! SSE SSE2 SSE3
(San Diego)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
?		939 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.4v		Socket 93964KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		114 million
0.09µm process
115mm² die

Athlon 64 ??? MMX 3DNow! SSE SSE2
(Victoria)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
[cancelled]		939 pins
?MHz (200x?)
(64-bit dual-pumped bus)
1.5v		Socket 93964KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		? million
0.09µm process
?mm² die

Athlon 64 3000+ MMX 3DNow! SSE SSE2
(Winchester)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
4Q 2004		939 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.4v		Socket 93964KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		68.5 million
0.09µm process
102mm² die
Athlon 64 3200+ MMX 3DNow! SSE SSE2
(Winchester)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
4Q 2004		939 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		Socket 93964KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		68.5 million
0.09µm process
102mm² die
Athlon 64 3500+ MMX 3DNow! SSE SSE2
(Winchester)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
4Q 2004		939 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.4v		Socket 93964KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		68.5 million
0.09µm process
102mm² die
Athlon 64 4200+ MMX 3DNow! SSE SSE2
(Winchester)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
[not released]		939 pins
?MHz (200x?)
(64-bit dual-pumped bus)
1.4v		Socket 93964KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		68.5 million
0.09µm process
102mm² die

Athlon 64 3000+ MMX 3DNow! SSE SSE2 SSE3
(Venice)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
May, 2005		939 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
?v		Socket 93964KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		114 million
0.09µm process
~120mm² die
Athlon 64 3200+ MMX 3DNow! SSE SSE2 SSE3
(Venice)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
May, 2005		939 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
?v		Socket 93964KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		114 million
0.09µm process
~120mm² die
Athlon 64 3500+ MMX 3DNow! SSE SSE2 SSE3
(Venice)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
May, 2005		939 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
?v		Socket 93964KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		114 million
0.09µm process
~120mm² die
Athlon 64 3800+ MMX 3DNow! SSE SSE2 SSE3
(Venice)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
May, 2005		939 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
?v		Socket 93964KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		114 million
0.09µm process
~120mm² die
AMD
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Athlon 64 X2 3800+ MMX 3DNow! SSE SSE2 SSE3
(Manchester)
(128-bit on-Die unbuffered DDR mem controller)
(dual core)
August 1, 2005 - {$354}		939 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		Socket 9392x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.09µm process
~147mm² die
Athlon 64 X2 4200+ MMX 3DNow! SSE SSE2 SSE3
(Manchester)
(128-bit on-Die unbuffered DDR mem controller)
(dual core)
May 31, 2005 - {$537}		939 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.4v		Socket 9392x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.09µm process
~147mm² die
Athlon 64 X2 4600+ MMX 3DNow! SSE SSE2 SSE3
(Manchester)
(128-bit on-Die unbuffered DDR mem controller)
(dual core)
May 31, 2005 - {$803}		939 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.4v		Socket 9392x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.09µm process
~147mm² die

Athlon 64 X2 4400+ MMX 3DNow! SSE SSE2 SSE3
(Toledo)
(128-bit on-Die unbuffered DDR mem controller)
(dual core)
May 31, 2005 - {$581}		939 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.4v		Socket 9392x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		233 million
0.09µm process
~199mm² die
Athlon 64 X2 4800+ MMX 3DNow! SSE SSE2 SSE3
(Toledo)
(128-bit on-Die unbuffered DDR mem controller)
(dual core)
May 31, 2005 - {$1001}		939 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.4v		Socket 9392x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		233 million
0.09µm process
~199mm² die
AMD
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Sempron 3000+ MMX 3DNow! SSE SSE2
(Palermo)
(128-bit on-Die unbuffered DDR mem controller)
June, 2006		939 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.4v		Socket 93964KB data (2-way)
64KB instruction (2-way)
128KB on-Die unified L2 (16-way exclusive)		77 million
0.09µm process
84mm² die
Sempron 3200+ MMX 3DNow! SSE SSE2
(Palermo)
(128-bit on-Die unbuffered DDR mem controller)
June, 2006		939 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.4v		Socket 93964KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		77 million
0.09µm process
84mm² die
Sempron 3400+ MMX 3DNow! SSE SSE2
(Palermo)
(128-bit on-Die unbuffered DDR mem controller)
June, 2006		939 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		Socket 93964KB data (2-way)
64KB instruction (2-way)
128KB on-Die unified L2 (16-way exclusive)		77 million
0.09µm process
84mm² die
Sempron 3500+ MMX 3DNow! SSE SSE2
(Palermo)
(128-bit on-Die unbuffered DDR mem controller)
June, 2006		939 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		Socket 93964KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		77 million
0.09µm process
84mm² die


Athlon 64 / Phenom (Socket AM2)
(NOT compatible with Socket 940 CPUs!)
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Athlon 64 LE 1600 MMX 3DNow! SSE SSE2 SSE3
(Orleans)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
2007		940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		81 million
0.09µm process
103mm² die
Athlon 64 LE 1620 MMX 3DNow! SSE SSE2 SSE3
(Orleans)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
2007		940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		81 million
0.09µm process
103mm² die
Athlon 64 LE 1640 MMX 3DNow! SSE SSE2 SSE3
(Orleans)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
2008		940 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		81 million
0.09µm process
103mm² die
Athlon 64 LE 1660 MMX 3DNow! SSE SSE2 SSE3
(Orleans)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
?		940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		81 million
0.09µm process
103mm² die
Athlon 64 3000+ MMX 3DNow! SSE SSE2 SSE3
(Orleans)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
May 23, 2006		940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		81 million
0.09µm process
103mm² die
Athlon 64 3200+ MMX 3DNow! SSE SSE2 SSE3
(Orleans)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
May 23, 2006		940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		81 million
0.09µm process
103mm² die
Athlon 64 3500+ MMX 3DNow! SSE SSE2 SSE3
(Orleans)
(128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max, AMD-V)
May 23, 2006 - {$189}		940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.25v or 1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		81 million
0.09µm process
103mm² die
Athlon 64 3800+ MMX 3DNow! SSE SSE2 SSE3
(Orleans)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
May 23, 2006 - {$290}		940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		81 million
0.09µm process
103mm² die
Athlon 64 4000+ MMX 3DNow! SSE SSE2 SSE3
(Orleans)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
February 20, 2007 - {$102}		940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		81 million
0.09µm process
103mm² die

Athlon 2650e MMX 3DNow! SSE SSE2 SSE3
(Lima)
(128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max, AMD-V)
November, 2008		940 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
?v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		77 million
0.065µm process
?mm² die
Athlon 64 3500+ EE MMX 3DNow! SSE SSE2 SSE3
(Lima)
(128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max, AMD-V)
February 20, 2007 - {$88}		940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.35v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		77 million
0.065µm process
?mm² die
Athlon 64 3800+ EE MMX 3DNow! SSE SSE2 SSE3
(Lima)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
February 20, 2007 - {$93}		940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		77 million
0.065µm process
?mm² die
AMD
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Athlon 64 X2 3800+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
May 23, 2006 - {$303}		940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.075v or 1.25v or
1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.09µm process
183mm² die
Athlon 64 X2 4000+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
May 23, 2006 - {$328}		940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.25v or 1.35v or
1.4v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		227 million
0.09µm process
235mm² die
Athlon 64 X2 4200+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max, AMD-V)
(dual core)
May 23, 2006 - {$365}		940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.25v or 1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.09µm process
183mm² die
Athlon 64 X2 4400+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max, AMD-V)
(dual core)
May 23, 2006 - {$470}		940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.25v or 1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		227 million
0.09µm process
235mm² die
Athlon 64 X2 4600+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
May 23, 2006 - {$558}		940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.25v or 1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.09µm process
183mm² die
Athlon 64 X2 4800+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
May 23, 2006 - {$645}		940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.25v or 1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		227 million
0.09µm process
235mm² die
Athlon 64 X2 5000+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max, AMD-V)
(dual core)
May 23, 2006 - {$696}		940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.25v or 1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.09µm process
183mm² die
Athlon 64 X2 5200+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V)
(dual core)
December 12, 2006 - {$403}		940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.25v or 1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		227 million
0.09µm process
235mm² die
Athlon 64 X2 5400+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC5800 mem controller, AMD-V)
(dual core)
December 12, 2006 - {$485}		940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.09µm process
183mm² die
Athlon 64 X2 5600+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V)
(dual core)
December 12, 2006 - {$505}		940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		227 million
0.09µm process
235mm² die
Athlon 64 X2 6000+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V)
(dual core)
February 20, 2007 - {$464}		940 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		227 million
0.09µm process
235mm² die
Athlon 64 X2 6400+ MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V)
(dual core)
2007		940 pins
3200MHz (200x16)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		227 million
0.09µm process
235mm² die

Athlon X2 BE 2300 MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
June 7, 2007 - {$86}		940 pins
1900MHz (200x9.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon X2 BE 2350 MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
June 7, 2007 - {$91}		940 pins
2100MHz (200x10.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon X2 BE 2400 MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
2007 - {$104}		940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon X2 3250e MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
November, 2008		940 pins
1500MHz (200x7.5)
(64-bit dual-pumped bus)
?v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon 64 X2 3600+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
March, 2007 - {$102}		940 pins
1900MHz (200x9.5)
(64-bit dual-pumped bus)
1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon 64 X2 4000+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
December 5, 2006		940 pins
2100MHz (200x10.5)
(64-bit dual-pumped bus)
1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon 64 X2 4050e MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
2Q 2008		940 pins
2100MHz (200x10.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon 64 X2 4200+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
2007		940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.325v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon 64 X2 4400+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
December 5, 2006
2007 - 1.375v		940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.35v, 1.375v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon 64 X2 4450e MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
2Q 2008		940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon 64 X2 4600+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
2008		940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.375v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon 64 X2 4800+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
December 5, 2006		940 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon 64 X2 4850e MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
April 3, 2008		940 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon 64 X2 5000+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
December 5, 2006		940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon 64 X2 5050e MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
December 15, 2008 - {$61}		940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.25v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon 64 X2 5200+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
2007		940 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
1.375v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon 64 X2 5400+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
3Q 2008 - {$87}		940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon 64 X2 5600+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
2008		940 pins
2900MHz (200x14.5)
(64-bit dual-pumped bus)
1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon 64 X2 5800+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
3Q 2008 - {$112}		940 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon 64 X2 6000+ MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
1H 2008		940 pins
3100MHz (200x15.5)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die

Athlon X2 ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V)
(dual core, HT 3.0, DICE)
[cancelled]		940 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		Socket AM2+2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		? million
0.065µm process
?mm² die

Athlon X2 7450 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Kuma)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(dual core, HT 3.0, DICE)
January 2009		940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
?v		Socket AM2+2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Athlon X2 7550 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Kuma)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(dual core, HT 3.0, DICE)
January 2009		940 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
?v		Socket AM2+2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Athlon X2 7750 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Kuma)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(dual core, HT 3.0, DICE)
December 15, 2008 - {$79}		940 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
?v		Socket AM2+2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Athlon X2 7850 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Kuma)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(dual core, HT 3.0, DICE)
April 28, 2009 - {$69}		940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Phenom 9500 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
November 19, 2007 - {$251}		940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.25v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom 9600 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
November 19, 2007 - {$283}		940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom 9700 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
[not released]		940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
?v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom 9900 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
[not released]		940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
?v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die

Phenom X3 8250e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(tri core, HT 3.0, DICE)
May 25, 2009 - {$122}		940 pins
1900MHz (200x9.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2+3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom X3 8400 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(tri core, HT 3.0, DICE)
March 27, 2008		940 pins
2100MHz (200x10.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2+3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom X3 8450e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(tri core, HT 3.0, DICE)
May 25, 2009 - {$122}		940 pins
2100MHz (200x10.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2+3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom X3 8450 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(tri core, HT 3.0, DICE)
April 23, 2008 - {$145}		940 pins
2100MHz (200x10.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2+3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom X3 8600 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(tri core, HT 3.0, DICE)
March 27, 2008		940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2+3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom X3 8650 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(tri core, HT 3.0, DICE)
April 23, 2008 - {$165}		940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2+3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom X3 8750 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(tri core, HT 3.0, DICE)
April 23, 2008 - {$195}		940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.25v		Socket AM2+3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom X3 8850 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(tri core, HT 3.0, DICE)
3Q 2009		940 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
?v		Socket AM2+3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die

Phenom X4 9100e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
March 27, 2008		940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.15v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom X4 9150e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
July 1, 2008 - {$175}		940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.125v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom X4 9350e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
July 1, 2008 - {$195}		940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.125v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom X4 9550 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
March 27, 2008 - {$209}		940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.25v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom X4 9650 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
March 27, 2008 - {$215}		940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom X4 9750 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
March 27, 2008 - {$215}		940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.25v or 1.3v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom X4 9850 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
March 27, 2008 - {$235}		940 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom X4 9950 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
July 1, 2008 - {$235}		940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.3v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die

Phenom X4 ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Ridgeback)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
[deneb for Socket AM2+]		940 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die

Phenom II X4 920 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
January 8, 2009 - {$235}		940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 940 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
January 8, 2009 - {$275}		940 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
AMD
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Sempron 2800+ MMX 3DNow! SSE SSE2 SSE3
(Manila)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
May 23, 2006		940 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
128KB on-Die unified L2 (16-way exclusive)		81 million
0.09µm process
103mm² die
Sempron 3000+ MMX 3DNow! SSE SSE2 SSE3
(Manila)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
May 23, 2006 - {$77}		940 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
1.25v or 1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		81 million
0.09µm process
103mm² die
Sempron 3200+ MMX 3DNow! SSE SSE2 SSE3
(Manila)
(128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max)
May 23, 2006 - {$87}		940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.25v or 1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
128KB on-Die unified L2 (16-way exclusive)		81 million
0.09µm process
103mm² die
Sempron 3400+ MMX 3DNow! SSE SSE2 SSE3
(Manila)
(128-bit on-Die unbuffered DDR2 PC5800 mem controller; 8GB max)
May 23, 2006 - {$97}		940 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
1.25v or 1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		81 million
0.09µm process
103mm² die
Sempron 3500+ MMX 3DNow! SSE SSE2 SSE3
(Manila)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
May 23, 2006 - {$109}		940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.25v or 1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
128KB on-Die unified L2 (16-way exclusive)		81 million
0.09µm process
103mm² die
Sempron 3600+ MMX 3DNow! SSE SSE2 SSE3
(Manila)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
May 23, 2006 - {$123}		940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		81 million
0.09µm process
103mm² die
Sempron 3800+ MMX 3DNow! SSE SSE2 SSE3
(Manila)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
2007? - {$108}		940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		81 million
0.09µm process
103mm² die

Sempron LE 1100 MMX 3DNow! SSE SSE2 SSE3
(Sparta)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
4Q 2007 - {$37}		940 pins
1900MHz (200x9.5)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		81 million
0.065µm process
?mm² die
Sempron LE 1150 MMX 3DNow! SSE SSE2 SSE3
(Sparta)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
4Q 2007 - {$42}		940 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
256KB on-Die unified L2 (16-way exclusive)		81 million
0.065µm process
?mm² die
Sempron LE 1200 MMX 3DNow! SSE SSE2 SSE3
(Sparta)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
4Q 2007 - {$48}		940 pins
2100MHz (200x10.5)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		81 million
0.065µm process
?mm² die
Sempron LE 1250 MMX 3DNow! SSE SSE2 SSE3
(Sparta)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
4Q 2007 - {$53}		940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		81 million
0.065µm process
?mm² die
Sempron LE 1300 MMX 3DNow! SSE SSE2 SSE3
(Sparta)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max)
2008 - {$41}		940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		81 million
0.065µm process
?mm² die

Sempron ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Spica)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(HT 3.0, DICE)
[cancelled]		940 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		Socket AM2+64KB data (2-way)
64KB instruction (2-way)
?KB on-Die unified L2 (16-way exclusive)		? million
0.065µm process
?mm² die


Phenom (Socket AM3)
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Athlon II X2 250u MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE)
2010		938 pins
1600MHz (200x8)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 260u MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
2010		938 pins
1800MHz (200x9)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 270u MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
3Q 2010		938 pins
2000MHz (200x10)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 215 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
3Q 2009		938 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 220 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
3Q 2010		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 235e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
October 20, 2009 - {$69}		938 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 240e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
October 20, 2009 - {$77}		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 240 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
July 23, 2009 - {$60}		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 245e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
May 10, 2010 - {$77}		938 pins
2900MHz (200x14.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 245 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
July 23, 2009 - {$66} 		938 pins
2900MHz (200x14.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 250e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
September 21, 2010		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 250 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
June 2, 2009 - {$87}		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 255 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
January 25, 2010 - {$74}		938 pins
3100MHz (200x15.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 260 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
May 10, 2010 - {$76}		938 pins
3200MHz (200x16)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 265 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
September 21, 2010 - {$76}		938 pins
3300MHz (200x16.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 270 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
2011?		938 pins
3400MHz (200x17)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die

Athlon II X3 400e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
October 20, 2009 - {$97}		938 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 405e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
October 20, 2009 - {$102}		938 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 415e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
May 10, 2010 - {$102}		938 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 420e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
September 21, 2010		938 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 425 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
October 20, 2009 - {$76}		938 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 435 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
October 20, 2009 - {$87}		938 pins
2900MHz (200x14.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 440 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
January 25, 2009 - {$84}		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 445 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
May 10, 2010 - {$87}		938 pins
3100MHz (200x15.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 450 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
September 21, 2010 - {$87}		938 pins
3200MHz (200x16)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X3 455 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Rana)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
December 7, 2010 - {$87}		938 pins
3300MHz (200x16.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die

Athlon II X4 600e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
October 20, 2009 - {$133}		938 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 605e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
October 20, 2009 - {$143}		938 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 610e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
May 10, 2010 - {$145}		938 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 615e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
September 21, 2010		938 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 620 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
September 16, 2009 - {$99}		938 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 630 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
September 16, 2009 - {$122}		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 635 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
January 25, 2010 - {$119}		938 pins
2900MHz (200x14.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 640 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
May 10, 2010 - {$122}		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 645 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
September 21, 2010 - {$122}		938 pins
3100MHz (200x15.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 650 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
2011?		938 pins
3200MHz (200x16)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die
Athlon II X4 665 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Propus)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
2011?		938 pins
3300MHz (200x16.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)		300 million
0.045µm process
169mm² die

Phenom II X2 545 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Callisto)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
June 2, 2009		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X2 550 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Callisto)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
June 2, 2009 - {$102}		938 pins
3100MHz (200x15.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X2 555 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Callisto)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
January 25, 2010 - {$99}		938 pins
3200MHz (200x16)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X2 560 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Callisto)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
September 21, 2010 - {$105}		938 pins
3300MHz (200x16.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X2 565 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Callisto)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
December 7, 2010 - {$115}		938 pins
3400MHz (200x17)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X2 570 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Callisto)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
May 3, 2011		938 pins
3500MHz (200x17.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X2 ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Callisto)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, HT 3.0, DICE, AMD-V)
2011?		938 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die

Phenom II X3 700e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Heka)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
June 2, 2009		938 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X3 705e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Heka)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
June 2, 2009 - {$125}		938 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X3 710 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Heka)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
February 9, 2009 - {$125}		938 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X3 720 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Heka)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
February 9, 2009 - {$145}		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Phenom II X3 740 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Heka)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(tri core, HT 3.0, DICE, AMD-V)
2011?		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die

Phenom II X4 805 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
February 9, 2009		938 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
4MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 810 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
February 9, 2009 - {$175}		938 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
4MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 820 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
1Q 2010		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
4MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 840 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
January 4, 2011 - {$102}		938 pins
3200MHz (200x16)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
4MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 900e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
June 2, 2009		938 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 905e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
June 2, 2009 - {$195}		938 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 910 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
February 9, 2009		938 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 910e MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
January 25, 2010 - {$169}		938 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 920 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
[not released]		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 925 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
2009		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 945 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
April 23, 2009 - {$225}		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 950 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
[not released]		938 pins
3100MHz (200x15.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 955 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
April 23, 2009 - {$245}		938 pins
3200MHz (200x16)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 960 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
2011?		938 pins
3300MHz (200x16.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 965 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
August 13, 2009 - {$245}		938 pins
3400MHz (200x17)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 970 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
September 21, 2010 - {$185}		938 pins
3500MHz (200x17.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 975 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
January 4, 2011 - {$195}		938 pins
3600MHz (200x18)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Phenom II X4 980 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V)
May 3, 2011 - {$185}		938 pins
3700MHz (200x18.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die

Phenom II X4 960T MMX 3DNow! SSE SSE2 SSE3 SSE4
(Zosma)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(quad core, HT 3.0, DICE, AMD-V, Turbo)
2011?		938 pins
3000MHz (200x15)
(3.4GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
4MB on-Die shared L3 (32-way)		904 million
0.045µm process
346mm² die

Phenom II X6 1035T MMX 3DNow! SSE SSE2 SSE3 SSE4
(Thuban)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(6 cores, HT 3.0, DICE, AMD-V, Turbo)
February 1, 2011		938 pins
2600MHz (200x13)
(3.1GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		6x 64KB data (2-way)
6x 64KB instruction (2-way)
6x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		904 million
0.045µm process
346mm² die
Phenom II X6 1045T MMX 3DNow! SSE SSE2 SSE3 SSE4
(Thuban)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(6 cores, HT 3.0, DICE, AMD-V, Turbo)
2011?		938 pins
2700MHz (200x13.5)
(3.2GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		6x 64KB data (2-way)
6x 64KB instruction (2-way)
6x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		904 million
0.045µm process
346mm² die
Phenom II X6 1055T MMX 3DNow! SSE SSE2 SSE3 SSE4
(Thuban)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(6 cores, HT 3.0, DICE, AMD-V, Turbo)
April 27, 2010 - {$199}		938 pins
2800MHz (200x14)
(3.3GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		6x 64KB data (2-way)
6x 64KB instruction (2-way)
6x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		904 million
0.045µm process
346mm² die
Phenom II X6 1065T MMX 3DNow! SSE SSE2 SSE3 SSE4
(Thuban)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(6 cores, HT 3.0, DICE, AMD-V, Turbo)
February 1, 2011 - {$185}		938 pins
2900MHz (200x14.5)
(3.4GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		6x 64KB data (2-way)
6x 64KB instruction (2-way)
6x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		904 million
0.045µm process
346mm² die
Phenom II X6 1075T MMX 3DNow! SSE SSE2 SSE3 SSE4
(Thuban)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(6 cores, HT 3.0, DICE, AMD-V, Turbo)
September 21, 2010 - {$245}		938 pins
3000MHz (200x15)
(3.5GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		6x 64KB data (2-way)
6x 64KB instruction (2-way)
6x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		904 million
0.045µm process
346mm² die
Phenom II X6 1090T MMX 3DNow! SSE SSE2 SSE3 SSE4
(Thuban)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(6 cores, HT 3.0, DICE, AMD-V, Turbo)
April 27, 2010 - {$295}		938 pins
3200MHz (200x16)
(3.6GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		6x 64KB data (2-way)
6x 64KB instruction (2-way)
6x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		904 million
0.045µm process
346mm² die
Phenom II X6 1100T MMX 3DNow! SSE SSE2 SSE3 SSE4
(Thuban)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(6 cores, HT 3.0, DICE, AMD-V, Turbo)
December 7, 2010 - {$265}		938 pins
3300MHz (200x16.5)
(3.7GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		6x 64KB data (2-way)
6x 64KB instruction (2-way)
6x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		904 million
0.045µm process
346mm² die
Phenom II X6 ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Thuban)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller)
(6 cores, HT 3.0, DICE, AMD-V, Turbo)
2011?		938 pins
?MHz (200x?)
(?GHz Turbo)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		6x 64KB data (2-way)
6x 64KB instruction (2-way)
6x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		904 million
0.045µm process
346mm² die

Sempron 140 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Sargas)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(HT 3.0, DICE, AMD-V)
July 23, 2009 - {$36}		938 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Sempron 145 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Sargas)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(HT 3.0, DICE, AMD-V)
3Q 2010 - {$36}		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Sempron 150 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Sargas)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(HT 3.0, DICE, AMD-V)
February 1, 2011		938 pins
2900MHz (200x14.5)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Sempron 180 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Sargas)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(HT 3.0, DICE, AMD-V)
2011?		938 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Sempron ??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Sargas)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(HT 3.0, DICE, AMD-V)
2011?		938 pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die


Phenom (Socket AM3+)
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Phenom II X4 ??? MMX 3DNow! SSE SSE2 SSE3 SSE4 AVX
(Orochi)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(quad core, HT 3.0, DICE, AMD-V, Turbo)
2011?		? pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		Socket AM3+4x 16KB data (4-way)
2x 64KB shared instruction (2-way)
2x 2MB on-Die shared L2 (16-way)
?MB on-Die shared L3 (?-way)		? million
0.032µm process
?mm² die

Phenom II X8 ??? MMX 3DNow! SSE SSE2 SSE3 SSE4 AVX
(Zambezi)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(8 cores, HT 3.0, DICE, AMD-V, Turbo)
2011?		? pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		Socket AM3+8x 16KB data (4-way)
4x 64KB shared instruction (2-way)
4x 2MB on-Die shared L2 (16-way)
8MB on-Die shared L3 (?-way)		? million
0.032µm process
?mm² die

Phenom II ??? MMX 3DNow! SSE SSE2 SSE3 SSE4 AVX
(Komodo)
(128-bit on-Die unbuffered DDR3 PC? mem controller)
(10 cores, HT 3.0, DICE, AMD-V, Turbo)
2012?		? pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		Socket AM3+10x 16KB data (4-way)
?x 64KB shared instruction (2-way)
?x ?MB on-Die shared L2 (16-way)
?MB on-Die shared L3 (?-way)		? million
?µm process
?mm² die


Business-Class Athlon / Phenom
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Athlon 1640B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
April 28, 2008 - {$50}		940 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		64KB data (2-way)
64KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die

Athlon X2 4450B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
April 28, 2008 - {$85}		940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon X2 4850B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
August 18, 2008		940 pins
2500MHz (200x12.5)
(64-bit dual-pumped bus)
1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon X2 5000B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
April 28, 2008 - {$95}		940 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.375v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon X2 5200B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
April 28, 2008 - {$110}		940 pins
2700MHz (200x13.5)
(64-bit dual-pumped bus)
1.375v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon X2 5400B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
April 28, 2008 - {$120}		940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die
Athlon X2 5600B MMX 3DNow! SSE SSE2 SSE3
(Brisbane)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller; 8GB max, AMD-V)
(dual core)
August 18, 2008		940 pins
2900MHz (200x14.5)
(64-bit dual-pumped bus)
1.35v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		154 million
0.065µm process
126mm² die

Athlon II X2 B22 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller, AMD-V)
(dual core, HT 3.0, DICE)
3Q 2009		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die
Athlon II X2 B24 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Regor)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller, AMD-V)
(dual core, HT 3.0, DICE)
3Q 2009		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		234 million
0.045µm process
118mm² die

Athlon II X2 B53 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Callisto)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller, AMD-V)
(dual core, HT 3.0, DICE)
3Q 2009		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Athlon II X2 B55 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Callisto)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller, AMD-V)
(dual core, HT 3.0, DICE)
3Q 2009		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die

Athlon II X3 B73 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Heka)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller, AMD-V)
(tri core, HT 3.0, DICE)
3Q 2009		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die
Athlon II X3 B75 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Heka)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller, AMD-V)
(tri core, HT 3.0, DICE)
3Q 2009		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
6MB on-Die shared L3 (32-way)		758 million
0.045µm process
258mm² die

Athlon II X4 B93 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
3Q 2009		938 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
4MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die
Athlon II X4 B95 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb)
(128-bit on-Die unbuffered DDR3 PC10666 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
3Q 2009		938 pins
3000MHz (200x15)
(64-bit dual-pumped bus)
?v		Socket AM2+
Socket AM3		4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
4MB on-Die shared L3 (48-way)		758 million
0.045µm process
258mm² die

Phenom X3 8600B MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(tri core, HT 3.0, DICE)
April 28, 2008 - {$175}		940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2+3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (?-way)		463 million
0.065µm process
288mm² die
Phenom X3 8750B MMX 3DNow! SSE SSE2 SSE3 SSE4
(Toliman)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(tri core, HT 3.0, DICE)
August 18, 2008		940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.25v		Socket AM2+3x 64KB data (2-way)
3x 64KB instruction (2-way)
3x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (?-way)		463 million
0.065µm process
288mm² die

Phenom X4 9600B MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
April 28, 2008 - {$230}		940 pins
2300MHz (200x11.5)
(64-bit dual-pumped bus)
1.25v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (?-way)		463 million
0.065µm process
288mm² die
Phenom X4 9750B MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena)
(128-bit on-Die unbuffered DDR2 PC8500 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
August 18, 2008		940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.25v		Socket AM2+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (?-way)		463 million
0.065µm process
288mm² die


Athlon 64 FX
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Athlon 64 FX-51 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
September 23, 2003 - {$733}		940 pins
2200MHz (200x11)
(64-bit dual-pumped bus)
1.5v		Socket 94064KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		106 million
0.13µm process
193mm² die
Athlon 64 FX-53 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die registered DDR PC3200 mem controller; 8GB max)
March 18, 2004 - {$733}		940 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v		Socket 94064KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		106 million
0.13µm process
193mm² die

Athlon 64 FX-53 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
June 1, 2004 - {$799}		939 pins
2400MHz (200x12)
(64-bit dual-pumped bus)
1.5v		Socket 93964KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		106 million
0.13µm process
193mm² die
Athlon 64 FX-55 MMX 3DNow! SSE SSE2
(Sledgehammer)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
October 19, 2004 - {$827}		939 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.5v		Socket 93964KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		106 million
0.13µm process
193mm² die

Athlon 64 FX-57 MMX 3DNow! SSE SSE2 SSE3
(San Diego)
(128-bit on-Die unbuffered DDR PC3200 mem controller; 8GB max)
June 27, 2005 - {$1031}		939 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.4v		Socket 93964KB data (2-way)
64KB instruction (2-way)
1MB on-Die unified L2 (16-way exclusive)		114 million
0.09µm process
115mm² die

Athlon 64 FX-60 MMX 3DNow! SSE SSE2 SSE3
(Toledo)
(128-bit on-Die unbuffered DDR mem controller)
(dual core)
January 10, 2006 - {$1031}		939 pins
2600MHz (200x13)
(64-bit dual-pumped bus)
1.35v		Socket 9392x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		233 million
0.09µm process
~199mm² die

Athlon 64 FX-62 MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 mem controller, AMD-V)
(dual core)
May 23, 2006 - {$1031}		940 pins
2800MHz (200x14)
(64-bit dual-pumped bus)
1.4v		Socket AM2
Socket AM2+		2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		227 million
0.09µm process
235mm² die

Athlon 64 FX-70 MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V)
(dual core)
November 30, 2006 - {$599}		1207 balls
2600MHz (200x13)
(64-bit dual-pumped bus)
1.4v		Socket F2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		227 million
0.09µm process
235mm² die
Athlon 64 FX-72 MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V)
(dual core)
November 30, 2006 - {$799}		1207 balls
2800MHz (200x14)
(64-bit dual-pumped bus)
1.4v		Socket F2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		227 million
0.09µm process
235mm² die
Athlon 64 FX-74 MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
November 30, 2006 - {$999}		1207 balls
3000MHz (200x15)
(64-bit dual-pumped bus)
1.4v		Socket F2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		227 million
0.09µm process
235mm² die
Athlon 64 FX-76 MMX 3DNow! SSE SSE2 SSE3
(Windsor)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller)
(dual core)
[not released]		1207 balls
3200MHz (200x16)
(64-bit dual-pumped bus)
1.4v		Socket F2x 64KB data (2-way)
2x 64KB instruction (2-way)
2x 1MB on-Die unified L2 (16-way exclusive)		227 million
0.09µm process
235mm² die

Phenom FX-80 MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena FX)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
[cancelled]		1207 balls
2200MHz (200x11)
(64-bit dual-pumped bus)
?v		Socket F+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die
Phenom FX-??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Agena FX)
(128-bit on-Die unbuffered DDR2 PC6400 mem controller, AMD-V)
(quad core, HT 3.0, DICE)
[cancelled]		1207 balls
?MHz (200x?)
(64-bit dual-pumped bus)
?v		Socket F+4x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
2MB on-Die shared L3 (32-way)		463 million
0.065µm process
288mm² die

Phenom FX-??? MMX 3DNow! SSE SSE2 SSE3 SSE4
(Deneb FX)
(128-bit on-Die unbuffered DDR3 PC? mem controller, AMD-V)
(quad core, HT 3.0, DICE)
[cancelled]		? pins
?MHz (200x?)
(64-bit dual-pumped bus)
?v		Socket AM34x 64KB data (2-way)
4x 64KB instruction (2-way)
4x 512KB on-Die unified L2 (16-way exclusive)
?MB on-Die shared L3 (32-way)		? million
0.045µm process
?mm² die


APUs
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
C-30
(Ontario)
(64-bit on-Die unbuffered DDR3 PC12800 mem controller)
(Radeon 6250 HD APU)
January 4, 2011		413 balls
1200MHz (200x6)
(64-bit dual-pumped bus)
?v		Socket FT132KB data (2-way)
32KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		? million
0.04µm process
?mm² die
C-50
(Ontario)
(64-bit on-Die unbuffered DDR3 PC12800 mem controller)
(dual core, Radeon 6250 HD APU)
January 4, 2011		413 balls
1000MHz (200x5)
(64-bit dual-pumped bus)
?v		Socket FT12x 32KB data (2-way)
2x 32KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		? million
0.04µm process
?mm² die
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
E-240
(Zacate)
(64-bit on-Die unbuffered DDR3 PC8500 mem controller)
(Radeon HD 6310 APU)
January 4, 2011		413 balls
1500MHz (200x7.5)
(64-bit dual-pumped bus)
?v		Socket FT132KB data (2-way)
32KB instruction (2-way)
512KB on-Die unified L2 (16-way exclusive)		? million
0.04µm process
75mm² die
E-300
(Zacate)
(64-bit on-Die unbuffered DDR3 PC8500 mem controller)
(dual core, Radeon HD 6310 APU)
3Q 2011		413 balls
1300MHz (200x6.5)
(64-bit dual-pumped bus)
?v		Socket FT12x 32KB data (2-way)
2x 32KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		? million
0.04µm process
75mm² die
E-350
(Zacate)
(64-bit on-Die unbuffered DDR3 PC8500 mem controller)
(dual core, Radeon HD 6310 APU)
January 4, 2011		413 balls
1600MHz (200x8)
(64-bit dual-pumped bus)
?v		Socket FT12x 32KB data (2-way)
2x 32KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		? million
0.04µm process
75mm² die
E-450
(Zacate)
(64-bit on-Die unbuffered DDR3 PC10666 mem controller)
(dual core, Radeon HD 6320 APU)
3Q, 2011		413 balls
1600MHz (200x8)
(64-bit dual-pumped bus)
?v		Socket FT12x 32KB data (2-way)
2x 32KB instruction (2-way)
2x 512KB on-Die unified L2 (16-way exclusive)		? million
0.04µm process
75mm² die
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
???
(Llano)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(APU, quad core)
2011?		? balls
?MHz (?x?)
(64-bit dual-pumped bus)
?v		Socket FM14x 32KB data (2-way)
4x 32KB instruction (2-way)
4x 1MB on-Die unified L2 (16-way exclusive)		? million
0.032µm process
?mm² die
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
???
(Krishna)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(APU, ? core)
2012?		? balls
?MHz (?x?)
(64-bit dual-pumped bus)
?v		Socket FM1?x 32KB data (2-way)
?x 32KB instruction (2-way)
?x ?MB on-Die unified L2 (16-way exclusive)		? million
0.028µm process
?mm² die
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
???
(Wichita)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(APU, ? core)
2012?		? balls
?MHz (?x?)
(64-bit dual-pumped bus)
?v		Socket FM1?x 32KB data (2-way)
?x 32KB instruction (2-way)
?x ?MB on-Die unified L2 (16-way exclusive)		? million
0.028µm process
?mm² die
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
???
(Richland)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(APU, ? core)
2012?		? balls
?MHz (?x?)
(64-bit dual-pumped bus)
?v		Socket FM1?x 32KB data (2-way)
?x 32KB instruction (2-way)
?x ?MB on-Die unified L2 (16-way exclusive)		? million
0.032µm process
?mm² die
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
???
(Weatherford)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(APU, dual core)
2012?		? balls
?MHz (?x?)
(64-bit dual-pumped bus)
?v		Socket FM12x 32KB data (2-way)
2x 32KB instruction (2-way)
2x ?MB on-Die unified L2 (16-way exclusive)		? million
0.032µm process
?mm² die
AMD
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
???
(Trinity)
(128-bit on-Die unbuffered DDR3 PC12800 mem controller)
(APU, quad core)
2012?		? balls
?MHz (?x?)
(64-bit dual-pumped bus)
?v		Socket FM14x 32KB data (2-way)
4x 32KB instruction (2-way)
4x ?MB on-Die unified L2 (16-way exclusive)		? million
0.032µm process
?mm² die


Intel Desktop


Core 2 (Socket 775)
Intel
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Celeron D 420 MMX SSE SSE2 SSE3
(Conroe-L)
(EM64T, NX bit)
June 3, 2007 - {$39}		775 balls
1600MHz (200x8)
(64-bit quad-pumped bus)
?v		Socket 77532KB data (8-way)
32KB instruction (8-way)
512KB on-Die unified L2 (2-way)		? million
0.065µm process
?mm² die
Celeron D 430 MMX SSE SSE2 SSE3
(Conroe-L)
(EM64T, NX bit)
June 3, 2007 - {$49}		775 balls
1800MHz (200x9)
(64-bit quad-pumped bus)
?v		Socket 77532KB data (8-way)
32KB instruction (8-way)
512KB on-Die unified L2 (2-way)		? million
0.065µm process
?mm² die
Celeron D 440 MMX SSE SSE2 SSE3
(Conroe-L)
(EM64T, NX bit)
June 3, 2007 - {$59}		775 balls
2000MHz (200x10)
(64-bit quad-pumped bus)
?v		Socket 77532KB data (8-way)
32KB instruction (8-way)
512KB on-Die unified L2 (2-way)		? million
0.065µm process
?mm² die
Celeron D 450 MMX SSE SSE2 SSE3
(Conroe-L)
(EM64T, NX bit)
August 31, 2008 - {$53}		775 balls
2000MHz (200x10)
(64-bit quad-pumped bus)
?v		Socket 77532KB data (8-way)
32KB instruction (8-way)
512KB on-Die unified L2 (2-way)		? million
0.065µm process
?mm² die

Celeron E1200 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
January 7, 2008		775 balls
1600MHz (200x8)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
512KB on-Die shared L2 (2-way)		291 million
0.065µm process
143mm² die
Celeron E1400 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
2Q 2008		775 balls
2000MHz (200x10)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
512KB on-Die shared L2 (2-way)		291 million
0.065µm process
143mm² die
Celeron E1500 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
December 1, 2008 - {$53}		775 balls
2200MHz (200x11)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
512KB on-Die shared L2 (2-way)		291 million
0.065µm process
143mm² die
Celeron E1600 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
June 3, 2009 - {$53}		775 balls
2400MHz (200x12)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
512KB on-Die shared L2 (2-way)		291 million
0.065µm process
143mm² die

Celeron E3200 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
September 8, 2009 - {$43}		775 balls
2400MHz (200x12)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (8-way)		228 million
0.045µm process
82mm² die
Celeron E3300 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
September 8, 2009 - {$53}		775 balls
2500MHz (200x12.5)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (8-way)		228 million
0.045µm process
82mm² die
Celeron E3400 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
January 17, 2010 - {$53}		775 balls
2600MHz (200x13)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (8-way)		228 million
0.045µm process
82mm² die
Celeron E3500 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
August 30, 2010 - {$52}		775 balls
2700MHz (200x13.5)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (8-way)		228 million
0.045µm process
82mm² die
Intel
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Pentium E2140 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
June 3, 2007 - {$74}		775 balls
1600MHz (200x8)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (4-way)		291 million
0.065µm process
143mm² die
Pentium E2160 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
June 3, 2007 - {$84}		775 balls
1800MHz (200x9)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (4-way)		291 million
0.065µm process
143mm² die
Pentium E2180 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
August 27, 2007 - {$84}		775 balls
2000MHz (200x10)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (4-way)		291 million
0.065µm process
143mm² die
Pentium E2200 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
December, 2007 - {$84}		775 balls
2200MHz (200x11)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (4-way)		291 million
0.065µm process
143mm² die
Pentium E2220 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit)
March 6, 2008		775 balls
2400MHz (200x12)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (4-way)		291 million
0.065µm process
143mm² die

Pentium E2210 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit)
2Q 2009		775 balls
2200MHz (200x11)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
1MB on-Die shared L2 (8-way)		228 million
0.045µm process
82mm² die

Pentium E5200 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit)
August 31, 2008 - {$84}		775 balls
2500MHz (200x12.5)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		228 million
0.045µm process
82mm² die
Pentium E5300 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit)
December 1, 2008 - {$86}		775 balls
2600MHz (200x13)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		228 million
0.045µm process
82mm² die
Pentium E5400 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit)
January 18, 2009 - {$84}		775 balls
2700MHz (200x13.5)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		228 million
0.045µm process
82mm² die
Pentium E5500 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit)
April 19, 2009 - {$75}		775 balls
2800MHz (200x14)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		228 million
0.045µm process
82mm² die
Pentium E5700 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit)
August 30, 2010 - {$75}		775 balls
3000MHz (200x15)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		228 million
0.045µm process
82mm² die
Pentium E6300 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
May 10, 2009 - {$84}		775 balls
2800MHz (266x10.5)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		228 million
0.045µm process
82mm² die
Pentium E6500 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
August, 2009 - {$84}		775 balls
2933MHz (266x11)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		228 million
0.045µm process
82mm² die
Pentium E6600 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
January 17, 2010 - {$84}		775 balls
3066MHz (266x11.5)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		228 million
0.045µm process
82mm² die
Pentium E6700 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
May 31, 2010 - {$86}		775 balls
3200MHz (266x12)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		228 million
0.045µm process
82mm² die
Pentium E6800 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT)
August 30, 2010 - {$86}		775 balls
3333MHz (266x12.5)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		228 million
0.045µm process
82mm² die
Intel
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Core 2 Duo E4300 MMX SSE SSE2 SSE3
(Allendale)
(dual core, EM64T, NX bit)
January 7, 2007 - ($183}		775 balls
1800MHz (200x9)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		167 million
0.065µm process
111mm² die
Core 2 Duo E4400 MMX SSE SSE2 SSE3
(Allendale)
(dual core, EM64T, NX bit)
April 22, 2007 - {$133}		775 balls
2000MHz (200x10)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		167 million
0.065µm process
111mm² die
Core 2 Duo E4500 MMX SSE SSE2 SSE3
(Allendale)
(dual core, EM64T, NX bit)
July 16, 2007		775 balls
2200MHz (200x11)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		167 million
0.065µm process
111mm² die
Core 2 Duo E4600 MMX SSE SSE2 SSE3
(Allendale)
(dual core, EM64T, NX bit)
October 22, 2007		775 balls
2400MHz (200x12)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		167 million
0.065µm process
111mm² die
Core 2 Duo E4700 MMX SSE SSE2 SSE3
(Allendale)
(dual core, EM64T, NX bit)
March 6, 2008		775 balls
2600MHz (200x13)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		167 million
0.065µm process
111mm² die

Core 2 Duo E6300 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 27, 2006 - ($183}		775 balls
1866MHz (266x7)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		291 million
0.065µm process
143mm² die
Core 2 Duo E6320 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
April 22, 2007 - {$163}		775 balls
1866MHz (266x7)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		291 million
0.065µm process
143mm² die
Core 2 Duo E6400 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 27, 2006 - ($224}		775 balls
2133MHz (266x8)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
2MB on-Die shared L2 (8-way)		291 million
0.065µm process
143mm² die
Core 2 Duo E6420 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
April 22, 2007 - {$183}		775 balls
2133MHz (266x8)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		291 million
0.065µm process
143mm² die
Core 2 Duo E6540 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 16, 2007		775 balls
2333MHz (333x7)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		291 million
0.065µm process
143mm² die
Core 2 Duo E6550 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT, TXT)
July 16, 2007 - {$163}		775 balls
2333MHz (333x7)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		291 million
0.065µm process
143mm² die
Core 2 Duo E6600 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 27, 2006 - ($316}		775 balls
2400MHz (266x9)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		291 million
0.065µm process
143mm² die
Core 2 Duo E6700 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 27, 2006 - ($530}		775 balls
2666MHz (266x10)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		291 million
0.065µm process
143mm² die
Core 2 Duo E6750 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT, TXT)
July 16, 2007 - {$183}		775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		291 million
0.065µm process
143mm² die
Core 2 Duo E6850 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT, TXT)
July 16, 2007 - {$266}		775 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		291 million
0.065µm process
143mm² die

Core 2 Duo E7200 MMX SSE SSE2 SSE3 SSE4
(Wolfdale 3M)
(dual core, EM64T, NX bit)
April, 2008 - {$133}		775 balls
2533MHz (266x9.5)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
3MB on-Die shared L2 (12-way)		228 million
0.045µm process
82mm² die
Core 2 Duo E7300 MMX SSE SSE2 SSE3 SSE4
(Wolfdale 3M)
(dual core, EM64T, NX bit)
August 11, 2008 - {$133}		775 balls
2666MHz (266x10)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
3MB on-Die shared L2 (16-way)		228 million
0.045µm process
82mm² die
Core 2 Duo E7400 MMX SSE SSE2 SSE3 SSE4
(Wolfdale 3M)
(dual core, EM64T, NX bit)
October 20, 2008 - {$133}		775 balls
2800MHz (266x10.5)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
3MB on-Die shared L2 (16-way)		228 million
0.045µm process
82mm² die
Core 2 Duo E7500 MMX SSE SSE2 SSE3 SSE4
(Wolfdale 3M)
(dual core, EM64T, NX bit)
January 18, 2009 - {$133}		775 balls
2933MHz (266x11)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
3MB on-Die shared L2 (16-way)		228 million
0.045µm process
82mm² die
Core 2 Duo E7600 MMX SSE SSE2 SSE3 SSE4
(Wolfdale 3M)
(dual core, EM64T, NX bit, VT)
June 3, 2009 - {$133}		775 balls
3066MHz (266x11.5)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
3MB on-Die shared L2 (16-way)		228 million
0.045µm process
82mm² die

Core 2 Duo E8190 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit)
January 7, 2008 - {$163}		775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		410 million
0.045µm process
107mm² die
Core 2 Duo E8200 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT, TXT)
January 7, 2008 - {$163}		775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		410 million
0.045µm process
107mm² die
Core 2 Duo E8300 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT, TXT)
April, 2008 - {$163}		775 balls
2833MHz (333x8.5)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		410 million
0.045µm process
107mm² die
Core 2 Duo E8400 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT, TXT)
January 7, 2008 - {$183}		775 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		410 million
0.045µm process
107mm² die
Core 2 Duo E8500 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT, TXT)
January 7, 2008 - {$266}		775 balls
3166MHz (333x9.5)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		410 million
0.045µm process
107mm² die
Core 2 Duo E8600 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT, TXT)
August 11, 2008 - {$266}		775 balls
3333MHz (333x10)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		410 million
0.045µm process
107mm² die
Core 2 Duo E8700 MMX SSE SSE2 SSE3 SSE4
(Wolfdale)
(dual core, EM64T, NX bit, VT, TXT)
January 18, 2009		775 balls
3500MHz (333x10.5)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		410 million
0.045µm process
107mm² die

Core 2 Duo ??? MMX SSE SSE2 SSE3 SSE4
(Ridgefield)
(dual core, EM64T, NX bit, VT)
[cancelled]		775 balls
?MHz (400x?)
(64-bit quad-pumped bus)
?v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
6MB on-Die shared L2 (24-way)		? million
0.045µm process
?mm² die
Intel
Processors		Natural
State		SocketsL1/L2 Cache
(Associativity)		Transistors
Core 2 Extreme X6800 MMX SSE SSE2 SSE3
(Conroe)
(dual core, EM64T, NX bit, VT)
July 27, 2006 - {$999}		775 balls
2933MHz (266x11)
(64-bit quad-pumped bus)
1.2v		Socket 7752x 32KB data (8-way)
2x 32KB instruction (8-way)
4MB on-Die shared L2 (16-way)		291 million
0.065µm process
143mm² die

Core 2 Quad-Q6400 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
[not released]		775 balls
2133MHz (266x8)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		582 million
0.065µm process
(2) 142mm² die
Core 2 Quad Q6600 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
January 8, 2007 - {$851}		775 balls
2400MHz (266x9)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		582 million
0.065µm process
(2) 142mm² die
Core 2 Quad Q6700 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
July 16, 2007 - {$530}		775 balls
2666MHz (266x10)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		582 million
0.065µm process
(2) 142mm² die
Core 2 Extreme QX6700 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
November 14, 2006 - {$999}		775 balls
2666MHz (266x10)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		582 million
0.065µm process
(2) 142mm² die
Core 2 Extreme QX6800 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT)
April 9, 2006 - {$1199}		775 balls
2933MHz (266x11)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		582 million
0.065µm process
(2) 142mm² die
Core 2 Extreme QX6850 MMX SSE SSE2 SSE3
(Kentsfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
July 16, 2007 - {$999}		775 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 4MB on-Die shared L2 (16-way)		582 million
0.065µm process
(2) 142mm² die

Core 2 Quad Q8200 MMX SSE SSE2 SSE3
(Yorkfield)
(quad core (dual die), EM64T, NX bit)
August 31, 2008 - {$224}		775 balls
2333MHz (333x7)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 2MB on-Die shared L2 (8-way)		820 million
0.045µm process
(2) 107mm² die
Core 2 Quad Q8200S MMX SSE SSE2 SSE3
(Yorkfield)
(quad core (dual die), EM64T, NX bit)
Janury 18, 2009 - {$245}		775 balls
2333MHz (333x7)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 2MB on-Die shared L2 (8-way)		820 million
0.045µm process
(2) 107mm² die
Core 2 Quad Q8300 MMX SSE SSE2 SSE3
(Yorkfield)
(quad core (dual die), EM64T, NX bit)
December 1, 2008 - {$224}		775 balls
2500MHz (333x7.5)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 2MB on-Die shared L2 (8-way)		820 million
0.045µm process
(2) 107mm² die
Core 2 Quad Q8400 MMX SSE SSE2 SSE3
(Yorkfield)
(quad core (dual die), EM64T, NX bit)
April 19, 2009 - {$183}		775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 2MB on-Die shared L2 (8-way)		820 million
0.045µm process
(2) 107mm² die
Core 2 Quad Q8400S MMX SSE SSE2 SSE3
(Yorkfield)
(quad core (dual die), EM64T, NX bit)
April 19, 2009 - {$245}		775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 2MB on-Die shared L2 (8-way)		820 million
0.045µm process
(2) 107mm² die

Core 2 Quad Q9300 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
January 7, 2008 - {$266}		775 balls
2500MHz (333x7.5)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 3MB on-Die shared L2 (12-way)		820 million
0.045µm process
(2) 107mm² die
Core 2 Quad Q9400 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
August 11, 2008 - {$266}		775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 3MB on-Die shared L2 (12-way)		820 million
0.045µm process
(2) 107mm² die
Core 2 Quad Q9400S MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
January 18, 2009 - {$320}		775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 3MB on-Die shared L2 (12-way)		820 million
0.045µm process
(2) 107mm² die
Core 2 Quad Q9450 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
January 7, 2008 - {$316}		775 balls
2666MHz (333x8)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		820 million
0.045µm process
(2) 107mm² die
Core 2 Quad Q9500 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT)
January 17, 2010 - {$183}		775 balls
2833MHz (333x8.5)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 3MB on-Die shared L2 (12-way)		820 million
0.045µm process
(2) 107mm² die
Core 2 Quad Q9505 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT)
September 8, 2009 - {$213}		775 balls
2833MHz (333x8.5)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 3MB on-Die shared L2 (12-way)		820 million
0.045µm process
(2) 107mm² die
Core 2 Quad Q9505S MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
September 8, 2009 - {$277}		775 balls
2833MHz (333x8.5)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 3MB on-Die shared L2 (12-way)		820 million
0.045µm process
(2) 107mm² die
Core 2 Quad Q9550 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
January 7, 2008 - {$530}		775 balls
2833MHz (333x8.5)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		820 million
0.045µm process
(2) 107mm² die
Core 2 Quad Q9550S MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
January 18, 2009 - {$369}		775 balls
2833MHz (333x8.5)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		820 million
0.045µm process
(2) 107mm² die
Core 2 Quad Q9650 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT, TXT)
August 11, 2008 - {$530}		775 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		820 million
0.045µm process
(2) 107mm² die
Core 2 Extreme QX9650 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT)
November 11, 2007 - {$999}		775 balls
3000MHz (333x9)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		820 million
0.045µm process
(2) 107mm² die
Core 2 Extreme QX9770 MMX SSE SSE2 SSE3 SSE4
(Yorkfield)
(quad core (dual die), EM64T, NX bit, VT)
March 24, 2008 - {$1399}		775 balls
3200MHz (400x8)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		820 million
0.045µm process
(2) 107mm² die

Core 2 Extreme QX9775 MMX SSE SSE2 SSE3 SSE4
(Harpertown)
(quad core (dual die), EM64T, NX bit, VT)
February 19, 2008 - {$1499}		771 balls
3200MHz (400x8)
(64-bit quad-pumped bus)
?v		Socket 7714x 32KB data (8-way)
4x 32KB instruction (8-way)
2x 6MB on-Die shared L2 (24-way)		820 million
0.045µm process
(2) 107mm² die

Core 2 Extreme QX???? MMX SSE SSE2 SSE3 SSE4
( ? )
(quad core, EM64T, NX bit, VT)
[cancelled]		775 balls
?MHz (?x?)
(64-bit quad-pumped bus)
?v		Socket 7754x 32KB data (8-way)
4x 32KB instruction (8-way)
4x ?MB on-Die unified L2 (?-way)		? million
0.045µm process
?mm² die


Core i7 (Nehalem)
Intel
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Pentium G6950 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(533MHz Intel HD GPU, dual core)
(EM64T, NX bit, VT)
January 7, 2010 - {$87}		1156 balls
2800MHz (133x21)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Pentium G6960 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(533MHz Intel HD GPU, dual core)
(EM64T, NX bit, VT)
January 9, 2011 - {$89}		1156 balls
2933MHz (133x22)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Intel
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Core i3 530 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT)
January 7, 2010 - {$113}		1156 balls
2933MHz (133x22)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i3 540 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT)
January 7, 2010 - {$133}		1156 balls
3066MHz (133x23)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i3 550 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT)
May 31, 2010 - {$138}		1156 balls
3200MHz (133x24)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i3 560 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT)
August 30, 2010 - {$138}		1156 balls
3333MHz (133x25)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}

Core i5 ??? MMX SSE SSE2 SSE3 SSE4.2
(Havendale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(GPU, dual core, SMT Hyperthreading, EM64T, NX bit, VT)
[cancelled]		1156 balls
?MHz (133x?)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		? million
0.045µm process
?mm² die
? million GPU {0.045µm - ?mm²}

Core i5 650 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
January 7, 2010 - {$176}		1156 balls
3200MHz (133x24)
(3.46GHz Turbo)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i5 655K MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
May 28, 2010 - {$216}		1156 balls
3200MHz (133x24)
(3.46GHz Turbo)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i5 660 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
January 7, 2010 - {$196}		1156 balls
3333MHz (133x25)
(3.6GHz Turbo)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i5 661 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(900MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
January 7, 2010 - {$196}		1156 balls
3333MHz (133x25)
(3.6GHz Turbo)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i5 670 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
January 7, 2010 - {$284}		1156 balls
3466MHz (133x26)
(3.73GHz Turbo)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}
Core i5 680 MMX SSE SSE2 SSE3 SSE4.2
(Clarkdale)
128-bit DDR3 on-Die unbuffered PC8500 mem controller
(733MHz Intel HD GPU, dual core)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
April 19, 2010 - {$294}		1156 balls
3600MHz (133x27)
(3.86GHz Turbo)
(64-bit bus)
?v		Socket 11562x 32KB data (8-way)
2x 32KB instruction (4-way)
2x 256KB on-Die unified L2 (8-way)
4MB on-Die shared L3 (16-way)		383 million
0.032µm process
81mm² die
177 million GPU {0.045µm - 114mm²}

Core i5 750 MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, EM64T, NX bit, VT, TXT, Turbo)
September 8, 2009 - {$196}		1156 balls
2666MHz (133x20)
(3.2GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die
Core i5 750S MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, EM64T, NX bit, VT, TXT, Turbo)
January 7, 2010 - {$259}		1156 balls
2400MHz (133x18)
(3.2GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die
Core i5 760 MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, EM64T, NX bit, VT, TXT, Turbo)
July 19, 2010 - {$205}		1156 balls
2800MHz (133x21)
(3.33GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die

Core i7 860 MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
September 8, 2009 - {$284}		1156 balls
2800MHz (133x21)
(3.46GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die
Core i7 860S MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
January 9, 2010 - {$337}		1156 balls
2800MHz (133x21)
(3.46GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die
Core i7 870 MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
September 8, 2009 - {$562}		1156 balls
2933MHz (133x22)
(3.6GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die
Core i7 870S MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
July 19, 2010 - {$351}		1156 balls
2666MHz (133x20)
(3.6GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die
Core i7 875K MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
May 28, 2010 - {$342}		1156 balls
2933MHz (133x22)
(3.6GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die
Core i7 880 MMX SSE SSE2 SSE3 SSE4.2
(Lynnfield)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
May 31, 2010 - {$583}		1156 balls
3066MHz (133x23)
(3.73GHz Turbo)
(64-bit bus)
?v		Socket 11564x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		774 million
0.045µm process
296mm² die
Intel
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Core i7 920 MMX SSE SSE2 SSE3 SSE4.2
(Bloomfield)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(quad core, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
November 17, 2008 - {$284}		1366 balls
2666MHz (133x20)
(2.93GHz Turbo)
(64-bit QPI)
?v		Socket 13664x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		731 million
0.045µm process
246mm² die
Core i7 930 MMX SSE SSE2 SSE3 SSE4.2
(Bloomfield)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(quad core, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
March 1, 2010 - {$294}		1366 balls
2800MHz (133x21)
(3.06GHz Turbo)
(64-bit QPI)
?v		Socket 13664x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		731 million
0.045µm process
246mm² die
Core i7 940 MMX SSE SSE2 SSE3 SSE4.2
(Bloomfield)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(quad core, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
November 17, 2008 - {$562}		1366 balls
2933MHz (133x22)
(3.2GHz Turbo)
(64-bit QPI)
?v		Socket 13664x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		731 million
0.045µm process
246mm² die
Core i7 950 MMX SSE SSE2 SSE3 SSE4.2
(Bloomfield)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(quad core, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
June 3, 2009 - {$562}		1366 balls
3066MHz (133x23)
(3.33GHz Turbo)
(64-bit QPI)
?v		Socket 13664x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		731 million
0.045µm process
246mm² die
Core i7 960 MMX SSE SSE2 SSE3 SSE4.2
(Bloomfield)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(quad core, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
October 18, 2009 - {$562}		1366 balls
3200MHz (133x24)
(3.46GHz Turbo)
(64-bit QPI)
?v		Socket 13664x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		731 million
0.045µm process
246mm² die

Core i7 ??? MMX SSE SSE2 SSE3 SSE4.2
(Gulftown)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(quad core, 2xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
[not released]		1366 balls
?MHz (?x?)
(?GHz Turbo)
(64-bit QPI)
?v		Socket 13664x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
?MB on-Die shared L3 (16-way)		1170 million
0.032µm process
240mm² die
Intel
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Core i7 965 Extreme MMX SSE SSE2 SSE3 SSE4.2
(Bloomfield)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(quad core, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
November 17, 2008 - {$999}		1366 balls
3200MHz (133x24)
(3.46GHz Turbo)
(64-bit QPI)
?v		Socket 13664x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		731 million
0.045µm process
246mm² die
Core i7 975 Extreme MMX SSE SSE2 SSE3 SSE4.2
(Bloomfield)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(quad core, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
June 3, 2009 - {$999}		1366 balls
3333MHz (133x25)
(3.6GHz Turbo)
(64-bit QPI)
?v		Socket 13664x 32KB data (8-way)
4x 32KB instruction (4-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (16-way)		731 million
0.045µm process
246mm² die

Core i7 970 MMX SSE SSE2 SSE3 SSE4.2
(Gulftown)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(6 cores, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
July 19, 2010 - {$885}		1366 balls
3200MHz (133x24)
(3.46GHz Turbo)
(64-bit QPI)
?v		Socket 13666x 32KB data (8-way)
6x 32KB instruction (4-way)
6x 256KB on-Die unified L2 (8-way)
12MB on-Die shared L3 (16-way)		1170 million
0.032µm process
240mm² die
Core i7 980X Extreme MMX SSE SSE2 SSE3 SSE4.2
(Gulftown)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(6 cores, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
March 15, 2010 - {$999}		1366 balls
3333MHz (133x25)
(3.6GHz Turbo)
(64-bit QPI)
?v		Socket 13666x 32KB data (8-way)
6x 32KB instruction (4-way)
6x 256KB on-Die unified L2 (8-way)
12MB on-Die shared L3 (16-way)		1170 million
0.032µm process
240mm² die
Core i7 990X Extreme MMX SSE SSE2 SSE3 SSE4.2
(Gulftown)
192-bit DDR3 on-Die unbuffered PC8500 mem controller
(6 cores, 1xQPI, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
February 14, 2011 - {$999}		1366 balls
3466MHz (133x26)
(3.73GHz Turbo)
(64-bit QPI)
?v		Socket 13666x 32KB data (8-way)
6x 32KB instruction (4-way)
6x 256KB on-Die unified L2 (8-way)
12MB on-Die shared L3 (16-way)		1170 million
0.032µm process
240mm² die


Core i7 (Sandy Bridge)
Intel
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Pentium G620 MMX SSE SSE2 SSE3 SSE4.2 AVX(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
May 23, 2011 - {$64}		1155 balls
2600MHz (100x26)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (4-way)		? million
0.032µm process
?mm² die
Pentium G620T MMX SSE SSE2 SSE3 SSE4.2 AVX(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
May 23, 2011 - {$70}		1155 balls
2200MHz (100x22)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (4-way)		? million
0.032µm process
?mm² die
Pentium G840 MMX SSE SSE2 SSE3 SSE4.2 AVX(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
May 23, 2011 - {$75}		1155 balls
2800MHz (100x28)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (4-way)		? million
0.032µm process
?mm² die
Pentium G850 MMX SSE SSE2 SSE3 SSE4.2 AVX(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT)
May 23, 2011 - {$86}		1155 balls
2900MHz (100x29)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (4-way)		? million
0.032µm process
?mm² die

Core i3 2100 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
February 20, 2011 - {$117}		1155 balls
3100MHz (100x31)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (4-way)		504 million
0.032µm process
149mm² die
Core i3 2100T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
February 20, 2011 - {$127}		1155 balls
2500MHz (100x25)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (4-way)		504 million
0.032µm process
149mm² die
Core i3 2105 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 3000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
May 23, 2011 - {$134}		1155 balls
3100MHz (100x31)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (4-way)		504 million
0.032µm process
149mm² die
Core i3 2120 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
February 20, 2011 - {$138}		1155 balls
3300MHz (100x33)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (4-way)		504 million
0.032µm process
149mm² die
Core i3 2120T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
3Q, 2011? - {$127}		1155 balls
2600MHz (100x26)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (4-way)		504 million
0.032µm process
149mm² die
Core i3 2125 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 3000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
3Q, 2011? - {$?}		1155 balls
3300MHz (100x33)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (4-way)		504 million
0.032µm process
149mm² die
Core i3 2130 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 850MHz Intel HD 2000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT)
3Q, 2011? - {$138}		1155 balls
3400MHz (100x34)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (4-way)		504 million
0.032µm process
149mm² die

Core i5 2390T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(dual core, 650MHz Intel HD 2000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
February 20, 2011 - {$195}		1155 balls
2700MHz (100x27)
(3.5GHz Turbo)
(64-bit bus)
?v		Socket 11552x 32KB data (8-way)
2x 32KB instruction (8-way)
2x 1.5k µops instruction (8-way)
2x 256KB on-Die unified L2 (8-way)
3MB on-Die shared L3 (4-way)		504 million
0.032µm process
149mm² die

Core i5 2300 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT, Turbo)
January 9, 2011 - {$177}		1155 balls
2800MHz (100x28)
(3.1GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (8-way)		995 million
0.032µm process
216mm² die
Core i5 2310 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT, Turbo)
May 23, 2011 - {$177}		1155 balls
2900MHz (100x29)
(?GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (8-way)		995 million
0.032µm process
216mm² die
Core i5 2400 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT, TXT, Turbo)
January 9, 2011 - {$184}		1155 balls
3100MHz (100x31)
(3.4GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (8-way)		995 million
0.032µm process
216mm² die
Core i5 2400S MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT, TXT, Turbo)
January 9, 2011 - {$195}		1155 balls
2500MHz (100x25)
(3.3GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (8-way)		995 million
0.032µm process
216mm² die
Core i5 2405S MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 3000 GPU)
(EM64T, NX bit, VT, TXT, Turbo)
May 23, 2011 - {$205}		1155 balls
2500MHz (100x25)
(3.3GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (8-way)		995 million
0.032µm process
216mm² die
Core i5 2500 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT, TXT, Turbo)
January 9, 2011 - {$205}		1155 balls
3300MHz (100x33)
(3.7GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (8-way)		995 million
0.032µm process
216mm² die
Core i5 2500K MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, Turbo)
January 9, 2011 - {$216}		1155 balls
3300MHz (100x33)
(3.7GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (8-way)		995 million
0.032µm process
216mm² die
Core i5 2500S MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT, TXT, Turbo)
January 9, 2011 - {$216}		1155 balls
2700MHz (100x27)
(3.7GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (8-way)		995 million
0.032µm process
216mm² die
Core i5 2500T MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 2000 GPU)
(EM64T, NX bit, VT, TXT, Turbo)
January 9, 2011 - {$216}		1155 balls
2300MHz (100x23)
(3.3GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (8-way)		995 million
0.032µm process
216mm² die

Core i5 ??? MMX SSE SSE2 SSE3 SSE4.2 AVX
("Ivy Bridge"-architecture)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, ?MHz Intel HD ? GPU)
(EM64T, NX bit, VT, TXT, Turbo)
2012?		1155 balls
?MHz (?x?)
(?GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
6MB on-Die shared L3 (8-way)		? million
0.022µm process
?mm² die

Core i7 2600 MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 3000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
January 9, 2011 - {$294}		1155 balls
3400MHz (100x34)
(3.8GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (12-way)		995 million
0.032µm process
216mm² die
Core i7 2600K MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 3000 GPU)
(SMT Hyperthreading, EM64T, NX bit, Turbo)
January 9, 2011 - {$317}		1155 balls
3400MHz (100x34)
(3.8GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (12-way)		995 million
0.032µm process
216mm² die
Core i7 2600S MMX SSE SSE2 SSE3 SSE4.2 AVX
(Sandy Bridge-DT)
128-bit DDR3 on-Die unbuffered PC10666 mem controller
(quad core, 850MHz Intel HD 3000 GPU)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
January 9, 2011 - {$306}		1155 balls
2800MHz (100x28)
(3.8GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (12-way)		995 million
0.032µm process
216mm² die

Core i7 ??? MMX SSE SSE2 SSE3 SSE4.2 AVX
("Ivy Bridge"-architecture)
128-bit DDR3 on-Die unbuffered PC12800 mem controller
(quad core, ?MHz Intel HD ? GPU)
(SMT Hyperthreading, EM64T, NX bit, VT, TXT, Turbo)
2012?		1155 balls
?MHz (?x?)
(?GHz Turbo)
(64-bit bus)
?v		Socket 11554x 32KB data (8-way)
4x 32KB instruction (8-way)
4x 1.5k µops instruction (8-way)
4x 256KB on-Die unified L2 (8-way)
8MB on-Die shared L3 (12-way)		? million
0.022µm process
?mm² die


Core i? ("Haswell")
Intel
Processors		Natural
State		SocketsL1/L2/L3 Cache
(Associativity)		Transistors
Core i? ??? MMX SSE SSE2 SSE3 SSE4.2 AVX
("Haswell"-architecture)
?-bit DDR? on-Die unbuffered PC? mem controller
(8 cores, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
2013?		? balls
?MHz (?x?)
(?GHz Turbo)
(64-bit bus)
?v		Socket ?8x ?KB data (?-way)
8x ?KB instruction (?-way)
8x ?k µops instruction (?-way)
8x ?KB on-Die unified L2 (?-way)
?MB on-Die shared L3 (?-way)		? million
0.022µm process
?mm² die

Core i? ??? MMX SSE SSE2 SSE3 SSE4.2 AVX
("Rockwell"-architecture)
?-bit DDR? on-Die unbuffered PC? mem controller
(8 cores, SMT Hyperthreading, EM64T, NX bit, VT, Turbo)
2013?		? balls
?MHz (?x?)
(?GHz Turbo)
(64-bit bus)
?v		Socket ?8x ?KB data (?-way)
8x ?KB instruction (?-way)
8x ?k µops instruction (?-way)
8x ?KB on-Die unified L2 (?-way)
?MB on-Die shared L3 (?-way)		? million
0.016µm process
?mm² die


Notes:
  • µ - micron (millionth of a meter).
  • Unified caches hold both data and instructions; shared caches are unified caches shared by more than one core.
  • The dates listed are official introduction dates. It does not necessarily mean those processors were available in quantity on that date. Processor names that are italicized in blue indicate a tenative release date based on various news articles, speculation, and sometimes pure rumor.
  • The prices listed with each processor are its price at the chip's introduction in US dollars. All prices are for quantities of 1000.
  • All bus speeds listed on this page are actual speeds; not DDR. The Athlon, Core, and Merced chips all use a dual (2x) or quad-pumped (4x) bus that hits on the rising and falling edges of the clock, yielding a faster effective bus speed. The quad-pumped bus works similar to that of AGP 4x mode (it uses a synchronous signal to double strobe each rising and falling edge).
  • Even though they have the same number of pins, Socket 940 and Socket AM2 CPUs are NOT interchangeable.

Posted by jmac at 6/25/2011 09:33:00 AM
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